Integrated circuits are fabricated by forming a layer, performing some type of processing in regard to that formed layer—such as etching—and then forming an overlying layer. This process is repeated many times until the completed integrated circuit is formed.
As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III–V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
One layer type that is commonly used is a dielectric or electrically insulating layer between two electrically conductive layers, such as metal layers. An oxide of some type, most commonly silicon dioxide, is often used to form the dielectric layer. These dielectric layers are used to electrically insulate the adjacent electrically conductive layers one from another. However, it is typically desirable to form a pattern of via holes through the dielectric layer after it is formed, and fill the via holes with an electrically conducting material, such as metal, so that selective electrical connections can be made between the overlying and underlying conductive layers, through the dielectric layers.
Such via holes are typically formed by an etching process of some type. A layer of photoresist is applied to the dielectric layer, and exposed and developed to produce a via hole pattern in the photoresist. The substrate is then subjected to a wet or dry etch, such as a physical ion or reactive ion etching process. The photoresist protects the dielectric layer from etching in those areas where the photoresist layer remains, but where the photoresist layer has been developed away, the dielectric layer etches in the via hole pattern.
Etching preferably continues until all of the via holes in the pattern have been etched to the desired depth. Unfortunately, for a variety of reasons, some of the via holes tend to etch at a different rate than others of the via holes. For example, those via holes that are grouped together in a relatively dense pattern of via holes tend to etch at a rate that is somewhat greater than those via holes that are in a relatively isolated pattern. If the dielectric layer is allowed to etch for a length of time that is sufficient to completely etch the relatively isolated via holes, then the relatively dense via holes tend to be over etched. Conversely, if the dielectric layer is etched for a length of time that is only sufficient to completely etch the relatively dense via holes, then the relatively isolated via holes tend to be under etched. In either case, the operation of the integrated circuit tends to be compromised.
Various etching parameters can be adjusted in order to reduce the difference in etch rate between the relatively dense via holes and the relatively isolated via holes. This difference is sometimes referred to a lag in the etch rate of the relatively isolated via holes. For example, the kind of gas that is used for the dry etching, the gas flow rates, the chamber pressure, the substrate temperature, and the processing power can all be adjusted in order to try to reduce the etch lag. However, these parameters all tend to also effect other characteristics of the etch process, such as the etch rate, etch selectively, and etch profiles, one or more of which may be deleterious to the process.
What is needed, therefore, is a method of etching relatively dense via holes and relatively isolated via holes in a manner that generally reduces problems such as those described above, at least in part.